Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then “wired,” or interconnected, together to define a specific electric circuit, such as an oscillator.
In mass-producing thousands of integrated circuits, each of which includes thousands or millions of interconnected transistors, the inevitable variances in fabricating each transistor mean that each circuit will not function exactly as intended by its designers. In fact, some of the circuits will operate slower than intended, and some of the devices will operate faster than intended. Those that operate too slow or too fast, that is, outside an acceptable range, will be discarded as waste. The percentage of the fabricated circuits that operate in the acceptable range define the manufacturing yield. A higher yield percentage means less waste and lower fabrication cost, whereas a lower yield percentage means greater waste and higher fabrication cost.
To determine whether a particular circuit can be economically produced in mass quantities, it is common practice for designers to ask fabricators to deliberately skew or alter the fabrication process to produce test sets of slow and fast circuits, known generally as skew lots. The fast and slow skew lots are made by skewing transistor dimensions, such as gate-insulator thickness (t) and channel length (L), to increase or decrease transconductance—a transistor property known to affect switching speed.
More precisely, since transconductance increases as the product of L and t decreases, fabricators reduce both L and t to make fast skew lots. Conversely, since transconductance decreases as the Lt product increases, they increase both L and t to make slow skew lots. Designers then test performance of these skew lots to predict or estimate the manufacturing yield of the circuit. The yield, in turn, tells designers whether the circuit design is acceptable or needs alterations to make fabrication more economical.
One problem that the present inventors identified with conventional skew lots is that for certain types of CMOS circuits (circuits that use complementary metal-oxide-semiconductor transistors), the performance of the fast and slow circuits is very similar, meaning that these skew lots are of little use in predicting manufacturing yield. For example, in conventional skew lots of CMOS oscillators (an oscillator is a circuit that outputs a signal that varies back and forth (continuously or discretely) between two voltage or current levels at a fixed or adjustable frequency), the speed of the so-called fast and slow oscillators were essentially identical in performance and thus were relatively useless in predicting yield for the oscillators.
Accordingly, the inventors recognized a need to devise new types of skew lots for CMOS oscillators and other types of circuits.